Encoding:

Format:

ADDQ[_S].PH 

ADDQ.PH   rd, rs, rt

ADDQ_S.PH rd, rs, rt

Purpose:

Add Fractional Halfword Vectors

Element-wise addition of two v ectors of Q15 fractional values to produce a vector of Q15 fractional results, with optional saturation.

Description:

rd = sign_extend(sat16(rs31..16 + rt31..16) || sat16(rs15..0 + rt15..0))

Each of the two right-most fractional halfword elements in register rt are added to the corresponding fractional halfword elements in register rs.

For the non-saturating version of the instruction, the result of each addition is written into the corresponding element in register rd. If the addition results in overflow or underflow, the result modulo 2 is written to the corresponding element in register rd.

For the saturating version of the instruction, signed saturating arithmetic is performed, where an overflow is clamped to the largest representable value (0x7FFF hexadecimal) and an underfl ow to th e smallest representable value

(0x8000 hexadecimal) before being written to the destination register rd.

For each instruction, the sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

For each instruction, if either of the individual additions result in underflow, overflow, or saturation, a 1 is written to bit 20 in the DSPControl register in the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQ.PH:
   tempB15..0 = add16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = add16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDQ_S.PH:
   tempB15..0 = satAdd16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = satAdd16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function add16( a15..0, b15..0 ) 
   temp16..0 = ( a15 || a15..0 ) + ( b15 || b15..0 )
   if ( temp16 != temp15 ) then
      DSPControlouflag:20 = 1
   endif
   return temp15..0
endfunction add16
function satAdd16( a15..0, b15..0 )
   temp16..0 = ( a15 || a15..0 ) + ( b15 || b15..0 )
   if ( temp16 != temp15 ) then
      if ( temp16 = 0 ) then
          temp15..0 = 0x7FFF
      else
          temp15..0 = 0x8000
      endif
      DSPControlouflag:20 = 1
   endif
   return temp15..0
endfunction satAdd16

Exceptions:

Reserved Instruction, DSP Disabled